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System
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CPU+ DSP Dual Core
CPU
· ARM cortex V7-A architecture CPU A5, Up to 800MHz
· Programmable memory management unit
· 32KB I-cache and 32KB D-cache
· Can accesses all device：Include DDR(up to 32MB)/ShareSRAM(up to 656KB)/SPI Nor/SPI SRAM
DSP
· VLIW & SIMD Architecture CEVA DSP X2, Up to 350MHz
· Support four 16×16-bit, two 32×16-bit, or two 32×32 MAC operations
· Two 32-bit multiply-accumulates
· 32KB I-cache ,32KB D-cache
· TCM：512KB P/DTCM，Programmable，shareable
· Can accesses all device：Include DDR(up to 32MB)/ShareSRAM(up to 656KB)/SPI Nor/SPI SRAM
· Neural network algorithm acceleration engine: providing CNN, DNN, RNN, RCNN, GRU, LRGP, LSTM, Feed Forward, MFCC, TANH, ReLU etc.
Neural network algorithm lib and api
Secure Subsystem
· Support AES-128/192/256 Encrypt & Decrypt in ECB/CTR/CBC/CBC-CTS mode
· Support SHA-1/224/256 mode with hardware padding
· Support hardware TRNG used to collects random bits from the ring oscillator or voltage, up to 64 random bits per time.
· Support 256bit Efuse
· Support CHIP unique ID, RSA, firmware encryption, firmware tampers proofing.
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Audio ADC
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· Build in 6 channals 24 bit input sigma-delta ADCs, SNR (A-WEIGHTING)>102dB, THD<-93dB.
· The input source can be selected from six MIC amplifiers and two AEC mix.
· ADC supports sample rate 8k/12k/11.025k/16k/22.05k/24k/32k/44.1k/48k/88.2k/96k/192KHz
· A digital high-pass filter can be used to remove dc offsets, and when the filter is applied as removing DC offset, its cut off frequency is configured
· Three option digital low-pass filter can be selected for vocie, sound or music application
· Support Auto Amplitude Limited.
· Supports single-ended input analog microphones and stereo full difference input microphone
· Supports 8 channals PDM Digital microphones
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Audio DAC
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· Build in stereo 24 bit sigma-delta DAC, SNR (A-WEIGHTING)>108dBA, THD<-90dB.
· DAC supports sample rate 8k/12k/11.025k/16k/22.05k/24k/32k/44.1/48kHz/88.2KHz/96kHz
· Build in stereo 20mW PA (Power Amplifier) for headphone
· Support digital volume of 256 steps with zero cross detection
· An anti-pop circuit for suppressing noise of PA when enable and disable
· Support differential audio output for speaker PA
· Support sample counter function
· Support mult-device output linkage mode
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Power &Clock Management
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PMU
· Supports Li-Ion battery power supply
· Linear regulators output VCC，AVCC，VDD，VDDR，SVCC
· Internal bandgap generates VREF form SVCC
· Actions’ ADP(Adaptive Dynamic Power) architecture integrated
· Multiple separate power domains, which can be power up/down by software based on
· Multiple power domain supported
· Multiple power state supported:S1,S2, S2VAD, S3
· 3.3V/1.8V I/O power and 1.0V core power
CMU
· Support two oscillator inputs: HOSC(24M) and LOSC(32K768)
· Support build-in HCL ( without 32k crystal) for low BOM cost mode
· Supply 6 PLLs for all modules and all the sources of the PLLs are HOSC. The 6 PLLs are COREPLL, DSPPLL，DDRPLL，DEVPLL，AUDIOPLL0 and AUDIOPLL1.
· DDRPLL/DEVPLL support spread spectrum
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