The BlueNRG-LP embeds a Cortex®-M0+ microcontroller that can operate up to 64 MHz and also the BlueNRG core coprocessor (DMA based) for Bluetooth Low Energy timing critical operations.
The main Bluetooth® Low Energy 5.2 specification supported features are:
2 Mbps data rate, long range (Coded PHY), advertising extensions, channel selection algorithm #2, GATT caching, hardware support for simultaneous connection, master/slave and multiple roles simultaneously, extended packet length support.
In addition, the BlueNRG-LP provides enhanced security hardware support by dedicated hardware functions:
True random number generator (RNG), encryption AES maximum 128-bit security co-processor, public key accelerator (PKA), CRC calculation unit, 48-bit unique ID, Flash memory read and write protection.
The BlueNRG-LP can be configured to support standalone or network processor applications. In the first configuration, the BlueNRG-LP operates as single device in the application for managing both the application code and the Bluetooth Low Energy stack.
The BlueNRG-LP embeds high-speed and flexible memory types:
Flash memory of 256 kB, RAM memory of 64 kB, one-time-programmable (OTP) memory area of 1 kB, ROM memory of 7 kB.
Direct data transfer between memory and peripherals and from memory-to-memory is supported by eight DMA channels with a full flexible channel mapping by the DMAMUX peripheral.
The BlueNRG-LP embeds a 12-bit ADC, allowing measurements of up to eight external sources and up to three internal sources, including battery monitoring and a temperature sensor.
The BlueNRG-LP has a low-power RTC and one advanced 16-bit timer.
The BlueNRG-LP features standard and advanced communication interfaces:
1x SPI, 2x SPI/I2S, 1x LPUART, 1x USART supporting ISO 7816 (smartcard mode), IrDA and Modbus mode, 2x I2C supporting SMBus/PMBus, 1x channel PDM.
The BlueNRG-LP operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications.
The BlueNRG-LP integrates a high efficiency SMPS step-down converter and an integrated PDR circuitry with a fixed threshold that generates a device reset when the VDD drops under 1.65 V.
The BlueNRG-LP comes in different package versions supporting up to:
32 I/Os for the QFN48 package, 20 I/Os for the QFN32 package, 30 I/Os for the WCSP49 package.
KEY FEATURES
- Bluetooth Low Energy system-on-chip supporting Bluetooth 5.2 specifications
- 2 Mbps data rate
- Long range (Coded PHY)
- Advertising extensions
- Channel selection algorithm #2
- GATT caching
- Radio
- RX sensitivity level: -97 dBm @ 1 Mbps, -104 dBm @ 125 kbps (long range)
- Programmable output power up to +8 dBm (at antenna connector)
- Data rate supported: 2 Mbps, 1 Mbps, 500 kbps and 125 kbps
- 128 physical connections
- Integrated balun
- Support for external PA
- BlueNRG core coprocessor (DMA based) for Bluetooth Low Energy timing critical operation
- 2.4 GHz proprietary radio driver
- Suitable for systems requiring compliance with the following radio frequency regulations: ETSI EN 300 328, EN 300 440, FCC CFR47 part 15, ARIB STD-T66
- Ultra-low power radio performance
- 10 nA in SHUTDOWN mode (1.8 V)
- 0.6 uA in DEEPSTOP mode (with external LSE and BLE wake-up sources, 1.8 V)
- 0.9 uA in DEEPSTOP mode (with internal LSI and BLE wake-up sources, 1.8 V)
- 4.3 mA peak current in TX (@ 0 dBm, 3.3 V)
- 3.4 mA peak current in RX (@ sensitivity level, 3.3V)
- High performance and ultra-low power Cortex-M0+ 32-bit, running up to 64 MHz
- Dynamic current consumption: 18 µA/MHz
- Operating supply voltage: from 1.7 to 3.6 V
- -40 ºC to 105 ºC temperature range
- Supply and reset management
- High efficiency embedded SMPS step-down converter with intelligent bypass mode
- Ultra-low power power-on-reset (POR) and power-down-reset (PDR)
- Programmable voltage detector (PVD)
- Clock sources
- Fail safe 32 MHz crystal oscillator with integrated trimming capacitors
- 32 kHz crystal oscillator
- Internal low-power 32 kHz RO
- On-chip non-volatile Flash memory of 256 kB
- On-chip RAM of 64 kB or 32 kB
- One-time-programmable (OTP) memory area of 1 kB
- Embedded UART bootloader
- Ultra-low power modes with or without timer and RAM retention
- Quadrature decoder
- Enhanced security mechanisms such as:
- Flash read/write protection
- SWD disabling
- Secure bootloader
- Security features
- True random number generator (RNG)
- Hardware encryption AES maximum 128-bit security co-processor
- HW public key accelerator (PKA)
- CRC calculation unit
- 48-bit unique ID
- System peripherals
- 1x DMA controller with 8 channels supporting ADC, SPI, I2C, USART and LPUART
- 1x SPI
- 2x SPI/I2S
- 2x I2C (SMBus/PMBus)
- 1x PDM (digital microphone interface)
- 1x LPUART
- 1x USART (ISO 7816 smartcard mode, IrDA, SPI Master and Modbus)
- 1x independent WDG
- 1x real time clock (RTC)
- 1x independent SysTick
- 1x 16-bit, 6 channel advanced timer
- Up to 32 fast I/Os
- 28 of them with wake-up capability
- 31 of them 5 V tolerant
- Analog peripherals
- 12-bit ADC with 8 input channels, up to 16 bits with a decimation filter
- Battery monitoring
- Analog watchdog
- Analog Mic I/F with PGA
- Development support
- Serial wire debug (SWD)
- 4 breakpoints and 2 watchpoints
- All packages are ECOPACK2 compliant
